5962-0924001VXC Datasheet, PDF (17/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

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ADS5400-SP
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
SDENB
SCLK
SDIO
Instruction Cycle
Data Transfer Cycle (s)
r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t_S (SDENB)
t_SCLK
SDENB
SCLK
SDIO
t_S (SDIO)
t_h (SDIO)
t_SCLKL
t_SCLKH
Figure 6. Serial Interface Write Timing Diagram
Figure 7 shows the serial interface timing diagram for a ADS5400 read operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from ADS5400 during the data transfer
cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from ADS5400 during
the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK
until the rising edge of SDENB when it will 3-state.
SDENB
SCLK
SDIO
Instruction Cycle
Data Transfer Cycle(s)
r/w N1 N0 - A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0
SDO
SDENB
SCLK
SDIO
SDO
D7 D6 D5 D4 D3 D2 D1 D0 0
3 pin Configuration Output
4 pin Configuration Output
Data n
Data n-1
t_d (Data)
Figure 7. Serial Interface Read Timing Diagram
Copyright © 2010–2012, Texas Instruments Incorporated
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