English
Language : 

5962-0924001VXC Datasheet, PDF (15/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter
◁
ADS5400-SP
www.ti.com
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
Table 2. PIN FUNCTIONS
NAME
PIN
NO.
DESCRIPTION
AINP, AINN
94, 95
Analog differential input signal (positive, negative). Includes 100-Ω differential load on-chip.
AVDD5
1, 76, 86, 90, 92,
97, 99
Analog power supply (5 V)
AVDD3
2, 7, 9, 85
Analog power supply (3.3 V)
DVDD3
24, 38, 50, 64 Output driver power supply (3.3 V)
AGND
3, 6, 8, 84, 88, 91,
93, 96, 98, 100
Analog Ground
DGND
25, 39, 51, 65 Digital Ground
CLKINP,
CLKINN
4, 5
Differential input clock (positive, negative). Includes 160-Ω differential load on-chip.
DA0N, DA0P
46, 47
Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DA1N–DA10N,
DA1P-DA10P
48-49, 52-59, 62-63,
66-73
Bus A, LVDS digital output pairs (bits 1- 10)
DA11N,
DA11P
74, 75
Bus A, LVDS digital output pair, most-significant bit (MSB)
CLKOUTAN,
CLKOUTAP
60, 61
Bus A, Clock Output (Data ready), LVDS output pair
DB0N, DB0P
40, 41
Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DB1N–DB10N,
DB1P-DB10P
14-23, 28-37
Bus B, LVDS digital output pairs (bits 1- 10)
DB11N,
DB11P
12, 13
Bus B, LVDS digital output pair, most-significant bit (MSB)
CLKOUTBN,
CLKOUTBP
26, 27
Bus B, Clock Output (Data ready), LVDS output pair
OVRAN,
OVRAP
44, 45
Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-
scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.
OVRBN,
OVRBP
42, 43
Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-
scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.
RESETN,
RESETP
10, 11
Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used
for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this
input also provides a SYNC time-stamp with the data sample present when RESET is clocked by
the ADC, as well as CLKOUT polarity reset. Includes 100-Ω differential load on-chip.
SCLK
78
Serial interface clock.
SDIO
79
Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers.
In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.
SDO
80
Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The
SDO pin is in high-impedance state in 3-pin interface mode (default).
SDENB
77
Active low serial data enable, always an input. Use to enable the serial interface. Internal 100kΩ
pull-up resistor.
VREF
87
Reference voltage input (2V nominal). A 0.1μF capacitor to AGND is recommended, but not
required.
ENA1BUS
81 (1)
Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr
0x02h bit<0>.
ENPWD
82 (1)
Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This
pin is logic OR'd with addr 0x05h bit<6>.
ENEXTREF
83 (1)
Enable External Reference Mode, active high. Device uses an external voltage reference when high.
This pin is logic OR'd with addr 0x05h bit<2>.
VCM
89
Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1μF
capacitor to AGND is recommended, but not required.
(1) This pin contains an internal ~40kΩ pull-down resistor, to ground.
Copyright © 2010–2012, Texas Instruments Incorporated
15
Product Folder Links: ADS5400-SP
 ▷