5962-0924001VXC Datasheet, PDF (36/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
www.ti.com
Figure 37 represents a scenario where an LVPECL output is used from a TI CDCM7005 with the clock signal
path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult to estimate and
requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of
insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC
is still not adequate. The total jitter at the CDCM7005 output depends heavily on the phase noise of the VCXO
selected. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further
conditioning, it is possible to clock the ADS5400 directly from the CDCM7005 using differential LVPECL outputs
(see the CDCM7005 data sheet for the exact schematic). A careful analysis of the required jitter and of the
components involved is recommended before determining the proper approach.
Low Jitter Clock Distribution
Board Master
Reference Clock
( High or Low Jitter)
10 MHz
Low Jitter Oscillator
1000 MHz
VCO
REF
LVPECL
LVPECL
or
LVCMOS
CDC
(Clock Distribution Chip)
Ex : TI CDCM7005
AMP and /or BPF optional , depending on jitter requirements
AMP
1000 MHz
SAW
XFMR
1000 MHz (To Transmit DAC )
125 MHz (To DSP )
CLKIN
CLKIN
ADC
TI ADS5400
250 MHz (To FPGA )
To Other
This is a general block diagram example: Consult the datasheet of the CDCM7005 for proper schematic
and for specifications regarding allowable input and output frequency and amplitude ranges .
Figure 37. Clock Source Diagram
36
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