5962-0924001VXC Datasheet, PDF (13/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
www.ti.com
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
Timing Diagrams (continued)
Sample N and RESET
pulse captured here
N+1
sampled
N N+1
output output
CLKINP
RESETP
t_RSU
t_RH
CLKOUTA is reset after 7.5 CLKIN cycles (+ tPD-CLKDIV4 )
tPD-CLKDIV4
CLKOUTAP
Phase 0: CLKOUT in desired
state after power up
Phase 1: misaligned by 1
clock after power up
Phase 2: misaligned by 2
clocks after power up
Phase 3: misaligned by 3
clocks after power up
CLKOUTBP
Phase 0: CLKOUT in desired
state after power up
Phase 1: misaligned by 1
clock after power up
Phase 2: misaligned by 2
clocks after power up
Phase 3: misaligned by 3
clocks after power up
CLKOUTB is reset after 6.5 CLKIN cycles (+ tPD-CLKDIV4 )
DATA BUS B
SYNCOUTB
(OVRB pins)
DATA BUS A
Latency of N and SYNCOUTB are matched to 7.5 CLKIN cycles
The phase of data shown prior to reset matches CLKOUTB in phase 0
If SYNC mode is enabled,
the OVRB pins become SYNCOUTB pins
The phase of data shown prior to reset matches CLKOUTA in phase 0
tPD-CLKDIV4
tPD-BDATA
t_su
t_h
N
N+2
Sync
N+1
Latency of N+1 is 7.5 CLKIN cycles
tPD-ADATA
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4
Copyright © 2010–2012, Texas Instruments Incorporated
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