5962-0924001VXC Datasheet, PDF (34/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
www.ti.com
80
f_IN = 10.05 MHz
75
f_IN = 100.33 MHz _{fIN = 901.13 MHz}
70
f_IN = 601.13 MHz
65
f_IN = 10.05 MHz f_IN = 100.33 MHz
f_IN = 601.13 MHz
60
65
60
f_IN = 801.13 MHz
55
f_IN = 1498.50 MHz
55
f_IN = 801.13 MHz
f_IN = 901.13 MHz
f_IN = 1498.50 MHz
50
50
45
45
f_s = 1 GSPS
40
0
0.2
0.4
0.6
0.8
1
1.2
Clock Amplitude - Vp-p
f_s = 1 GSPS
40
0
0.2
0.4
0.6
0.8
1
1.2
Clock Amplitude - Vp-p
Figure 32. ADS5400 SFDR vs Differential Clock
Level
Figure 33. ADS5400 SNR vs Differential Clock
Level
The characterization of the ADS5400 is typically performed with a 1.5 V_PP differential clock, but the ADC
performs well with a differential clock amplitude down to ~400mV_PP (200mV swing on both CLK and CLK), as
shown in Figure 32 and Figure 33. For jitter-sensitive applications, the use of a differential clock has some
advantages at the system level and is strongly recommended. The differential clock allows for common-mode
noise rejection at the printed circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the
ADC is better for jitter-sensitive, high-frequency applications because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At
high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small
amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the
uncertainty in the sampling point associated with a slow slew rate. Figure 34 demonstrates a recommended
method for converting a single-ended clock source into a differential clock; it is similar to the configuration found
on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data
Converters (SLYT075) for more details.
0.1 mF
Clock
Source
CLK
ADS5400
CLK
Figure 34. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.5 V using internal 400Ω resistors (see
Figure 30). It is recommended to use ac coupling in the clock path, but if this scheme is not possible, the
ADS5400 features good tolerance to clock common-mode variation, as shown in Figure 35 and Figure 36. The
internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal
should be provided.
34
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