5962-0924001VXC Datasheet, PDF (20/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
Address (hex)
BIT 7
Table 8. Serial Register 0x02 (Read or Write)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
0x02
Coarse Clock Phase Adjustment bits<4:0>
0
Defaults
0
0
0
0
0
0
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BIT 1
Clock Divider
0
BIT 0
Single or
Dual Bus
0
BIT <0>
0
1
BIT <1>
0
1
BIT <2>
0
1
BIT <7:3>
Address (hex)
0x03
Defaults
Single or Dual Bus Output Selection
dual bus output (A and B)
single bus output (A)
Output Clock Divider
CLKOUT equals CLKIN divide by 4 (not available in single bus mode)
CLKOUT equals CLKIN divide by 2
RESERVED
set to 0 if writing this register
do not set to 1
Input Clock Coarse Phase Adjustment
Use as a coarse adjustment of input clock phase. The 5-bit adjustment
provides a step size of ~2.4ps across a range from code 00000 = 0 ps
to code 11111 = 73ps.
BIT 7
0
Table 9. Serial Register 0x03 (Read or Write)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Fine Clock Phase Adjustment bits<5:0>
0
0
0
0
0
BIT 1
0
0
BIT 0
Analog Offset
bit<8>
factory set
BIT <0>
BIT <1>
0
1
BIT <7:2>
Analog Offset control (most significant bit of 9-bit word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120µV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
RESERVED
set to 0 if writing this register
do not set to 1
Fine Clock Phase Adjustment
Use as a fine adjustment of the input clock phase. The 6-bit
adjustment provides a step resolution of ~116fs across a range from
code 000000 = 0ps to code 111111 = 7.4ps. Can be used in conjuction
with Coarse Clock Phase Adjustment in address 0x02.
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