5962-0924001VXC Datasheet, PDF (21/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
www.ti.com
Address (hex)
0x04
Defaults
BIT 7
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
Table 10. Serial Register 0x04 (Read or Write)
BIT 6
BIT 5
BIT 4
BIT 3
Analog Offset Control bits<7:0>
factory set
BIT 2
BIT 1
BIT 0
BIT <7:0>
Analog Offset control continued (least significant bits of 9-bit
word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
Performance of the ADC is not specified across the entire offset
control range. Some performance degradation is expected as larger
offsets are programmed.
Address (hex)
0x05
Defaults
BIT 7
Table 11. Serial Register 0x05 (Read or Write)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Temp Sensor Powerdown reserved Sync Mode Data Format Reference
0
0
1
0
0
0
BIT 1
Stagger
Output
0
BIT 0
0
0
BIT <0>
0
1
BIT <1>
0
1
BIT <2>
0
1
BIT <3>
0
1
BIT <4>
0
1
RESERVED
set to 0 if writing this register
do not set to 1
Stagger Output Bus
Output bus A and B aligned
Output bus A and B staggered (see timing diagrams)
Enable External Reference
Enable internal reference
Enable external reference
Set Data Output Format
Enable offset binary
Enable two's complement
Set Sync Mode
Disable data synchronization mode
Enable data synchronization mode
When enabled, the OVR pin(s) are replaced with SYNC output
signal(s). The SYNC output signal is time-aligned with the output data
matching the corresponding input sample and RESET input pulse
Copyright © 2010–2012, Texas Instruments Incorporated
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