DS90UB929-Q1 Datasheet, PDF (51/71 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer

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DS90UB929-Q1
SNLS457 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
101
ADD
(hex)
0x65
Register Name
Pattern
Generator
Configuration
102
0x66 PGIA
103
0x67 PGID
Bit(s)
7
6
5
4
3
2
1
0
7:0
7:0
Table 8. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x00
0x00
Function
Description
Checkerboard
Scale
Custom
Checkerboard
PG 18–bit
Mode
External Clock
Timing Select
Color Invert
Auto Scroll
PG Indirect
Address
PG Indirect
Data
Reserved.
Scale Checkered Patterns:
0: Normal operation (each square is 1x1 pixel) (default).
1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels).
Setting this bit gives better visibility of the checkered patterns.
Use Custom Checkerboard Color:
0: Use white and black in the Checkerboard pattern (default).
1: Use the Custom Color and black in the Checkerboard pattern.
18-bit Mode Select:
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness
(default).
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of
brightness and the R, G, and B outputs use the six most significant color bits.
Select External Clock Source:
0: Selects the internal divided clock when using internal timing (default).
1: Selects the external pixel clock when using internal timing.
This bit has no effect in external timing mode (PATGEN_TSEL = 0).
Timing Select Control:
0: The Pattern Generator uses external video timing from the pixel clock, Data Enable,
Horizontal Sync, and Vertical Sync signals (default).
1: The Pattern Generator creates its own video timing as configured in the Pattern
Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.
See TI App Note AN-2198.
Enable Inverted Color Patterns:
0: Do not invert the color output (default).
1: Invert the color output.
See TI App Note AN-2198.
Auto Scroll Enable:
0: The Pattern Generator retains the current pattern (default).
1: The Pattern Generator will automatically move to the next enabled pattern after the
number of frames specified in the Pattern Generator Frame Time (PGFT) register.
See TI App Note AN-2198.
This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It
should be written prior to reading or writing the Pattern Generator Indirect Data register.
See TI App Note AN-2198
When writing to indirect registers, this register contains the data to be written. When
reading from indirect registers, this register contains the read back value.
See TI App Note AN-2198
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