DS90UB929-Q1 Datasheet, PDF (43/71 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer

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DS90UB929-Q1
SNLS457 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
32
ADD
(hex)
0x20
Register Name
Deserializer
Capabilities 1
33
0x21 Deserializer
Capabilities 2
38
0x26 Link Detect
Control
Bit(s)
1
0
7:2
1:0
7:3
2:0
Table 8. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
Default
(hex)
0x00
0x00
Function
Description
VID_24B_HD_
AUD
Deserializer supports 24-bit video concurrently with HD audio.
This field is automatically configured by the Bidirectional Control Channel once RX Lock
has been detected. Software may overwrite this value, but must also set the FREEZE
DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
DES_CAP_FC
_GPIO
Deserializer supports GPIO in the Forward Channel Frame.
This field is automatically configured by the Bidirectional Control Channel once RX Lock
has been detected. Software may overwrite this value, but must also set the FREEZE
DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
Reserved.
Reserved.
Reserved.
LINK DETECT
TIMER
Bidirectional Control Channel Link Detect Timer.
This field configures the link detection timeout period. If the timer expires without valid
communication over the reverse channel, link detect will be deasserted.
000: 162 microseconds.
001: 325 microseconds.
010: 650 microseconds.
011: 1.3 milliseconds.
100: 10.25 microseconds.
101: 20.5 microseconds.
110: 41 microseconds.
111: 82 microseconds.
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