DS90UB929-Q1 Datasheet, PDF (30/71 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer

DS90UB929-Q1
SNLS457 – NOVEMBER 2014
www.ti.com
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 18
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 18. Start And Stop Conditions
To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 25 and a WRITE is shown in Figure 26.
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 19. Serial Control Bus — Read
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 20. Serial Control Bus — Write
The I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface
requirements and throughput considerations, please refer to TI Application Note SNLA131.
8.5.2 Multi-Master Arbitration Support
The Bidirectional Control Channel in the FPD-Link III devices implements I2C compatible bus arbitration in the
proxy I2C master implementation. When sending a data bit, each I2C master senses the value on the SDA line.
If the master is sending a logic 1 but senses a logic 0, the master has lost arbitration. It will stop driving SDA,
retrying the transaction when the bus becomes idle. Thus, multiple I2C masters may be implemented in the
system.
If the system does require master-slave operation in both directions across the BCC, some method of
communication must be used to ensure only one direction of operation occurs at any time. The communication
method could include using available read/write registers in the deserializer to allow masters to communicate
with each other to pass control between the two masters. An example would be to use register 0x18 or 0x19 in
the deserializer as a mailbox register to pass control of the channel from one master to another.
8.5.3 I2C Restrictions on Multi-Master Operation
The I2C specification does not provide for arbitration between masters under certain conditions. The system
should make sure the following conditions cannot occur to prevent undefined conditions on the I2C bus:
• One master generates a repeated Start while another master is sending a data bit.
• One master generates a Stop while another master is sending a data bit.
30
Submit Documentation Feedback
Product Folder Links: DS90UB929-Q1
Copyright © 2014, Texas Instruments Incorporated