DS90UB929-Q1 Datasheet, PDF (39/71 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer

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DS90UB929-Q1
SNLS457 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
20
ADD
(hex)
0x14
Register Name
BIST Control
21
0x15 I2C Voltage
Select
22
0x16 BCC Watchdog
Control
23
0x17 I2C Control
Bit(s)
7:3
2:1
0
7:0
7:1
0
7
6:4
3:0
Table 8. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x01
0xFE
0x1E
Function
Description
OSC Clock
Source
BIST Enable
I2C Voltage
Select
Timer Value
Timer Control
I2C Pass All
SDA Hold
Time
I2C Filter
Depth
Reserved.
Allows choosing different OSC clock frequencies for forward channel frame.
OSC clock frequency in functional mode when TMDS clock is not present and 0x03[2]=1:
00: 50 MHz oscillator.
01: 50 MHz oscillator.
10: 100 MHz oscillator.
11: 25 MHz oscillator.
Clock source in BIST mode i.e. when 0x14[0]=1:
00: External pixel clock.
01: 33 MHz oscillator.
1x: 100 MHz oscillator.
BIST control:
0: Disabled (default).
1: Enabled.
Selects 1.8 or 3.3V for the I2C_SDA and I2C_SCL pins. This register is loaded from the
I2C_VSEL strap option from the SCLK pin at power-up. At power-up, a logic LOW will
select 3.3V operation, while a logic HIGH (pull-up resistor attached) will select 1.8V
signaling.
Reads of this register return the status of the I2C_VSEL control:
0: Select 1.8V signaling.
1: Select 3.3V signaling.
This bit may be overwritten via register access or via eFuse program by writing an 8-bit
value to this register:
Write 0xb5 to set I2C_VSEL.
Write 0xb6 to clear I2C_VSEL.
The watchdog timer allows termination of a control channel transaction if it fails to
complete within a programmed amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set
to 0.
Disable Bidirectional Control Channel (BCC) Watchdog Timer:
0: Enable BCC Watchdog Timer operation (default).
1: Disable BCC Watchdog Timer operation.
0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs
matching either the remote Deserializer Slave ID or the remote Slave ID (default).
1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs
that do not match the Serializer I2C Slave ID.
Internal SDA hold time:
Configures the amount of internal hold time provided for the SDA input relative to the
SCL input. Units are 40 nanoseconds.
Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be
rejected. Units are 5 nanoseconds.
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