HD3SS3220_15 Datasheet, PDF (30/43 Pages) Texas Instruments – HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

HD3SS3220
SLLSES1 – DECEMBER 2015
10 Layout
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10.1 Layout Guidelines
10.1.1 Suggested PCB Stackups
TI recommends a PCB of at least six layers. Table 15 provides example PCB stackups.
Table 15. Example PCB Stackups
6-LAYER
SIGNAL
GROUND
SIGNAL ⁽¹⁾
SIGNAL ⁽¹⁾
POWER/GROUND ⁽²⁾
SIGNAL
8-LAYER
SIGNAL
GROUND
SIGNAL
SIGNAL
POWER/GROUND ⁽²⁾
SIGNAL
GROUND
SIGNAL
10-LAYER
SIGNAL
GROUND
SIGNAL ⁽¹⁾
SIGNAL ⁽¹⁾
POWER
POWER/GROUND ⁽²⁾
SIGNAL ⁽¹⁾
SIGNAL ⁽¹⁾
GROUND
SIGNAL
(1) Route directly adjacent signal layers at a 90° offset to each other
(2) Plane may be split depending on specific board considerations. Ensure that traces on adjacent planes do not cross splits.
10.1.2 High-Speed Signal Trace Length Matching
Match the etch lengths of the relevant differential pair traces of each interface. The etch length of the differential
pair groups do not need to match (that is, the length of the transmit pair does not need to match the length of the
receive pair). When matching the intrapair length of the high-speed signals, add serpentine routing to match the
lengths as close to the mismatched ends as possible. See Figure 13 for more details.
Length-Matching at Matched Ends
Length-Matching at Mismatched Ends
Figure 13. Length Matching
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