HD3SS3220_15 Datasheet, PDF (18/43 Pages) Texas Instruments – HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

HD3SS3220
SLLSES1 – DECEMBER 2015
www.ti.com
7.5 Programming
For further programmability, the HD3SS3220 can be controlled using I²C. The HD3SS3220 local I²C interface is
available for reading/writing after x clock cycles when the device is powered up. The SCL and SDA terminals are
used for I²C clock and I²C data respectively. If I²C is the preferred method of control, the ADDR pin must be set
accordingly.
Table 5. HD3SS3220 I²C Target Address
ADDR pin
H
L
Bit 7 (MSB)
1
1
Bit 6
1
0
Bit 5
0
0
Bit 4
0
0
Bit 3
1
1
Bit 2
1
1
Bit 1
1
1
Bit 0 (W/R)
0/1
0/1
The following procedure should be followed to write to HD3SS3220 I²C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the HD3SS3220 7-bit
address and a zero-value R/W bit to indicate a write cycle.
2. The HD3SS3220 device acknowledges the address cycle.
3. The master presents the sub-address (I²C register within the HD3SS3220 device) to be written, consisting of
one byte of data, MSB-first.
4. The HD3SS3220 device acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The HD3SS3220 device acknowledges the byte transfer.
7. The master can continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the HD3SS3220 device.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the HD3SS3220 I²C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the HD3SS3220 7-bit
address and a one-value R/W bit to indicate a read cycle.
2. The HD3SS3220 device acknowledges the address cycle.
3. The HD3SS3220 device transmits the contents of the memory registers MSB-first starting at register 00h or
last read sub-address+1. If a write to the I²C register occurred prior to the read, then the HD3SS3220 device
starts at the sub-address specified in the write.
4. The HD3SS3220 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the
master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the HD3SS3220 device transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I²C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the HD3SS3220 7-bit
address and a zero-value R/W bit to indicate a read cycle.
2. The HD3SS3220 device acknowledges the address cycle.
3. The master presents the sub-address (I²C register within the HD3SS3220 device) to be read, consisting of
one byte of data, MSB-first.
4. The HD3SS3220 device acknowledges the sub-address cycle.
5. The master terminates the read operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, then the reads start at register
offset 00h and continue byte-by-byte through the registers until the I²C master terminates
the read operation. If a I²C address write occurred prior to the read, then the reads start at
the sub-address specified by the address write.
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