HD3SS3220_15 Datasheet, PDF (27/43 Pages) Texas Instruments – HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

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HD3SS3220
SLLSES1 – DECEMBER 2015
8.2.3.1 Design Requirements
For this design example, use the parameters shown in Table 13.
VDD5
PARAMETER
System_VBUS
I²C I/O Supply
VCC33
AC Coupling Capacitors for SS signals
Pull-up Resistors: DIR, ID, INT_N,
VCONN_FAULT_N
Pull-up Resistors: I²C
Pull-up Resistors: CURRENT_MODE
Decoupling Capacitors: VCONN Bulk
Decoupling Capacitors: VBUS Bulk
Table 13. Design Parameters, DFP Port
EXAMPLE
5.25 V
5.25 V
3.3 V
3.3 V
100 nF
200 K
4.7 K
10 K
100 μF
150 μF
COMMENTS
VDD5 is used to provide VCONN power to CC pins. Value of this supply
should be ≥ 5 V to keep VCONN ≥ 4.75 V.
VDD5 and System_VBUS can be shorted together; however careful
consideration is needed to maintain desired VBUS and VCONN for the Type-C
port.
1.8 V is also an option.
When using the 3.3-V supply, the customer must ensure that the VDD is 3 V
and above. Otherwise the I²C may back power the device
3-3.6 V range allowed.
75-200 nF range allowed.
For TX pairs only, RX pairs will be biased by host Receiver. Note that
HD3SS3220 requires a common mode biasing of 0-2 V. If host receiver has
bias voltage outside this range, appropriate additional ac coupling caps and
biasing of HD3SS3220 RX pairs needed.
Smaller values can be used, but leakage needs to be considered for device
power budget calculations.
Example here is for 3 A. If 1.5 A or 900 mA needed different values are
required.
8.2.3.2 Detailed Design Procedure
HD3SS3220 can be used to design a USB Type-C DFP Port. An example schematic for DFP implementation is
illustrated in Figure 11.
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