HD3SS3220_15 Datasheet, PDF (29/43 Pages) Texas Instruments – HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

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HD3SS3220
SLLSES1 – DECEMBER 2015
8.2.4.1 Design Requirements
For this design example, use the parameters shown in Table 14.
VDD5
PARAMETER
I²C I/O Supply
VCC33
AC Coupling Capacitors for SS signals
Pull-up Resistors: DIR, INT_N
Pull-up Resistors: I²C
Series resistor: VBUS_DET
Table 14. Design Parameters, UFP Port
EXAMPLE
5V
3.3 V
3.3 V
100 nF
200 K
4.7 K
900 K
COMMENTS
VBUS from Type-C port can be used.
1.8 V is also an option.
When using the 3.3-V supply, the customer must ensure that the VDD is 3 V
and above. Otherwise the I²C may back power the device
3-3.6 V range allowed.
75-200 nF range allowed.
For TX pairs only, RX pairs will be biased by host Receiver. Note that
HD3SS3220 requires a common mode biasing of 0-2 V. If host receiver has
bias voltage outside this range, appropriate additional ac coupling caps and
biasing of HD3SS3220 RX pairs needed.
Smaller values can be used, but leakage needs to be considered for device
power budget calculations.
8.2.4.2 Detailed Design Procedure
HD3SS3220 can be used to design a USB Type-C DFP Port. An example schematic for UFP implementation is
illustrated in Figure 12.
9 Power Supply Recommendations
HD3SS3220 has 4.5 to 5.5-V supply voltage requirement. The device can be powered from the same rail that
provides power for V_(BUS).
Copyright © 2015, Texas Instruments Incorporated
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