HD3SS3220_15 Datasheet, PDF (22/43 Pages) Texas Instruments – HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

HD3SS3220
SLLSES1 – DECEMBER 2015
www.ti.com
7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
Figure 8. General Control Register
7
6
DEBOUNCE
5
4
MODE_SELECT
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
I2C_SOFT
_RESET
R/U
2
1
SOURCE_PREF
R/W
0
DISABLE
_TERM
R/W
Table 10. General Control Register Field Descriptions
Bit Field
7:6 DEBOUNCE
5:4 MODE_SELECT
3
I2C_SOFT _RESET
2:1 SOURCE_PREF
0
DISABLE _TERM
Type
R/W
Reset
2’b00
R/W
2’b00
R/U
1’b0
R/W
2’b00
R/W
1’b0
Description
The nominal amount of time the HD3SS3220 debounces the
voltages on the CC pins.
00 – 168 ms (Default)
01 – 118 ms
10 – 134 ms
11 – 152 ms
This register can be written to set the HD3SS3220 mode
operation. The ADDR pin must be set to I²C mode. If the default
is maintained, HD3SS3220 shall operate according to the PORT
pin levels and modes. The MODE_SELECT can only be
changed when in the unattached state.
00 – DRP mode (start from unattached.SNK) (default)
01 – UFP mode (unattached.SNK)
10 – DFP mode (unattached.SRC)
11 – DRP mode (start from unattached.SNK)
This register resets the digital logic. The bit is self-clearing. A
write of 1 starts the reset. The following registers can be
affected after setting this bit:
CURRENT_MODE_DETECT
ACTIVE_CABLE_DETECTION
ACCESSORY_CONNECTED
ATTACHED_STATE
CABLE_DIR
This field controls the TUSB322I behavior when configured as a
DRP.
00 – Standard DRP (default)
01 – DRP performs Try.SNK
10 – Reserved
11 – DRP performs Try.SRC
This field disables the termination on CC pins and transition the
CC state machine to the disabled state.
0 – Termination enabled according TUSB322I mode of operation
(default)
1 – Termination disabled and state machine held in disable state
7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
Figure 9. Device Revision Register
7
6
5
4
3
2
1
0
REVISION
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
7:0 REVISION
Table 11. Device Revision Register Field Descriptions
Type
R
Reset
‘h02
Description
Revision of HD3SS3220. Defaults to 0x02
22
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