LMG3410 Datasheet, PDF (20/33 Pages) Texas Instruments – 600-V 12-A Single Channel GaN Power Stage

LMG3410
SNOSD10A – APRIL 2016 – REVISED JUNE 2016
11 Layout
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11.1 Layout Guidelines
The layout of the LMG3410 is critical to its performance and functionality. Because the half-bridge configuration
is typically used with these GaN devices, layout recommendations will be considered with this configuration. A
four-layer or higher layer count board is required to reduce the parasitic inductances of the layout to achieve
suitable performance.
11.1.1 Power Loop Inductance
The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes
large di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic
interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
This loop inductance is minimized by locating the power devices as close together as possible. The bus
capacitance is positioned in line with the two devices, either below the low-side device or above the high-side
device, on the same side of the PCB. The return path (PGND in this case) is located on the second layer on the
PCB in close proximity to the top layer. By using an inner layer and not the bottom layer, the vertical dimension
of the loop is reduced, thus minimizing inductance. A large number of vias near both the device terminal and bus
capacitance carries the high-frequency switching current to the inner layer while minimizing impedance.
11.1.2 Ground Connection
The LMG3410 features a signal ground “GND” connection along with the source connection. The GND pin
should be directly connected to SOURCE underneath the package on the PCB. In addition, the return path for
the passives associated to the driver (e.g. bypass capacitance) must be connected to the GND plane. Isolate the
GND plane from the high-current SOURCE plane except the connection at the GND pin and the thermal vias
under the package. In Figure 16, local GND planes are located on the second copper layer to act as the return
for the local circuitry.
11.1.3 Bypass Capacitors
The gate drive loop impedance must also be minimized to yield strong performance. Although the gate driver is
integrated on package, the bypass capacitance for the driver is on board. As the GaN device is turned off to a
negative voltage, the impedance of the negative source is included in the crucial turn-off path. As the critical
hold-off path passes through this external bypass capacitor attached to V_NEG, this capacitor must be located
close to the LMG3410. In the Figure 16, V_NEG bypass capacitors C12 and C22 are located immediately adjacent
to the pins on the IC with a direct connection to the GND net.
The bypass capacitors for the input supply and the 5V regulator must also be located immediately next to the IC
with a close connection to the ground plane.
11.1.4 Switch-Node Capacitance
GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching
loss. To preserve this low switching loss, additional capacitance added to the output node must be minimized.
The PCB capacitance at the switch node can be minimized by following these guidelines:
• Minimize overlap between the switch-node plane and other power and ground planes
• Thin the GND return path under the high-side device somewhat while still maintaining a low-inductance path
• Choose high-side isolator ICs and bootstrap diodes with low capacitance
• Locate the power inductor as close to the power stage as possible
• Power inductors should be constructed with a single-layer winding to minimize intra-winding capacitance
• If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and
the power stage to effectively shield the power stage from the additional capacitance
• If a back-side heat-sink is used, restrict the switch-node copper coverage on the bottom copper layer to the
minimum area necessary to extract the needed heat
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