LMG3410 Datasheet, PDF (12/33 Pages) Texas Instruments – 600-V 12-A Single Channel GaN Power Stage

LMG3410
SNOSD10A – APRIL 2016 – REVISED JUNE 2016
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8.3 Feature Description
The LMG3410 includes numerous features to provide increased switching performance and efficiency in
customers' applications while providing an easy-to-use solution.
8.3.1 Direct-Drive GaN Architecture
The LMG3410 utilizes a series FET to ensure the GaN module stays off when V_DD is not applied. When this FET
is off, the gate of the GaN transistor is held within a volt of the FET's source. This structure allows the LMG3410
to hold off voltage when the device is off by turning the GaN transistor off through its source. As the silicon FET
blocks the drain voltage, the V_GS of the GaN transistor decreases until it passes its threshold voltage. Then, the
GaN transistor turns off and blocks the remaining drain voltage.
When the LMG3410 is powered up, the internal buck-boost converter generates a negative voltage (V_NEG) that is
sufficient to directly turn off the GaN transistor. In this case, the silicon FET is held on and the GaN transistor is
gated directly with the negative voltage.
8.3.2 Internal Buck-Boost DC-DC Converter
An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the GaN
device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation,
the converter remains in discontinuous-conduction mode, but may enter continuous-conduction mode during
startup and overload conditions. The converter is controlled internally and requires only a single surface-mount
inductor and output bypass capacitor. For recommendations on the required passives, see Buck-Boost Converter
Design.
8.3.3 Internal Auxiliary LDO
An internal low-dropout regulator is provided to supply external loads, such as digital isolators for the high-side
drive signal. It is capable of delivering up to 5 mA to an external load. A bypass capacitor with 1 µF typical is
required for stability.
8.3.4 Fault Detection
The GaN driver includes built-in over-current protection (OCP), over-temperature protection (OTP) and under
voltage lockout (UVLO).
The OCP circuit monitors the LMG3410's drain current through the integrated silicon MOSFET and compares
that current signal with an internally-set limit. Upon actuation of the over-current detection circuit, the GaN FET is
shut off and held off until power is reset or the fault is reset by holding the input low for 500 microseconds.
The over-temperature protection circuit measures the temperature of the driver die and trips if the temperature
exceeds the over-temperature threshold (typically 165 °C). Upon an over-temperature condition, the GaN device
is held off until temperature falls below the hysteresis limit, typically 15 degrees below the turn-off threshold.
The FAULT output is a push-pull output indicating the readiness and fault status of the driver. It is held low when
starting up until the safety FET is turned on. In an OCP or OTP fault condition, it is held low until the fault latches
are reset or fault is cleared. If the power supplies go below the UVLO thresholds, power transistor switching is
disabled and FAULT is held low until the power supplies recover.
8.3.5 Drive Strength Adjustment
To allow for an adjustable slew rate to control stability and ringing in the circuit, as well as an adjustment to pass
electro-magnetic compliance standards, LMG3410 allows the user to adjust its drive strength. A resistor is
connected the RDRV pin and ground. The value of the resistor determines the slew rate of the device; see
Figure 2 for the relationship between RDRV and the drain slew rate. The propagation delays vary with RDRV;
consult Figure 1 for more details.
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