LMG5200_15 Datasheet, PDF (9/23 Pages) Texas Instruments – GaN TECHNOLOGY PREVIEWLMG5200 80-V, GaN Half-Bridge Power Stage

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Propagation Delay and Mismatch Measurement (continued)
LMG5200
SNOSCY4A – MARCH 2015 – REVISED MARCH 2015
50%
HI
V_IN
SW
10%
V_IN
2
Time
Figure 6. High-Side Gate Driver Turn-On
HI
50%
50%
LI
V_IN
SW
2
10%
GND
Time
Figure 7. Low-Side Gate Driver Turn-On
LI
50%
SW
V_IN
10%
V_IN(clamp)
Figure 8. High-Side Gate Driver Turn-Off
V_IN(clamp)
SW
10%
GND
Time
Figure 9. Low-Side Gate Driver Turn-Off
8 Detailed Description
8.1 Overview
Figure 10 shows the LMG5200, half-bridge, GaN power stage with a highly integrated high-side and low-side
gate drivers which includes built in UVLO protection circuitry and a over voltage clamp circuitry. The clamp
circuitry limits the bootstrap refresh operation to ensure that the high-side gate driver overdrive does not exceed
5.4 V. The device integrates two, 18-mΩ GaN FETs in a half-bridge configuration. The device can be used in
many isolated and non-isolated topologies allowing very simple integration. The package is designed to minimize
the loop inductance while keeping the PCB design simple. The drive strengths for turn-on and turn-off are
optimized to ensure high voltage slew rates without causing any excessive ringing on the gate or power loop.
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