LMG5200_15 Datasheet, PDF(10/23 Page) Texas Instruments – GaN TECHNOLOGY PREVIEWLMG5200 80-V, GaN Half-Bridge Power Stage

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LMG5200_15 Datasheet, PDF (10/23 Pages) Texas Instruments – GaN TECHNOLOGY PREVIEWLMG5200 80-V, GaN Half-Bridge Power Stage

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LMG5200

SNOSCY4A â MARCH 2015 â REVISED MARCH 2015

www.ti.com

8.2 Functional Block Diagram

Figure 10 shows the functional block diagram of the LMG5200 device with integrated high-side and low-side GaN

FETs.

LMG5200

VCC 6

HI 4

UVLO and

Clamp

Level

Shifter

2 HB

1 VIN

3 HS

UVLO

8 SW

LI 5

9 PGND

7 AGND

Figure 10. Functional Block Diagram

8.3 Feature Description

The LMG5200 device brings ease of designing high power density boards without the need for underfill while

maintaining creepage and clearance requirements. The propagation delays between the high-side gate driver

and low-side gate driver are matched to allow very tight control of dead time. Controlling the dead time is critical

in GaN-based applications to maintain high efficiency. HI and LI can be independently controlled to minimize the

third quadrant conduction of the low-side FET for hard switched buck converters. A very small propagation

mismatch between the HI and LI to the drivers for both the falling and rising thresholds ensures dead times of

<10 ns. Co-packaging the GaN FET half-bridge with the driver ensures minimized common source inductance.

This minimized inductance has a significant performance impact on hard-switched topologies.

The built in bootstrap circuit with clamp prevents the high-side gate drive from exceeding the GaN FETs

maximum gate-to-source voltage (Vgs) without any additional external circuitry. The built-in driver has an

undervoltage lockout (UVLO) on the VDD and bootstrap (HB-HS) rails. When the voltage is below the UVLO

threshold voltage, the device ignores both the HI and LI signals to prevent the GaN FETs from being partially

turned on. Below UVLO, if there is sufficient voltage (VVCC > 2.5 V), the driver actively pulls the high-side and

low-side gate driver output low. The UVLO threshold hysteresis of 200 mV prevents chattering and unwanted

turn-on due to voltage spikes. Use an external VCC bypass capacitor with a value of 0.1 ÂµF or higher. A size of

0402 is recommended to minimize trace length to the pin. Place the bypass and bootstrap capacitors as close to

the device as possible to minimize parasitic inductance.

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