LMG5200_15 Datasheet, PDF (11/23 Pages) Texas Instruments – GaN TECHNOLOGY PREVIEWLMG5200 80-V, GaN Half-Bridge Power Stage

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LMG5200
SNOSCY4A – MARCH 2015 – REVISED MARCH 2015
Feature Description (continued)
8.3.1 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side gate drive, dc bias power for HB undervoltage
lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be
calculated using Equation 1.
C_BST
>
æ Q_gH
çç
è
+ I_HB
+ t_ON(max)
DV
+ Q_rr
ö
÷÷
ø
where
• I_HB is the quiescent current of the high-side gate driver (100 µA, max)
• t_ON(max) is the maximum on-time period of the high-side gate driver
• Q_rr is the reverse recovery charge of the bootstrap diode
• QgH is the gate charge of the high-side GaN FET
• ΔV is the permissible ripple in the bootstrap capacitor (< 100 mV, typ)
(1)
A 100-nF, 16-V, 0402 ceramic capacitor is suitable for most applications. Place the bootstrap capacitor as close
to the HB and HS pins as possible.
8.3.2 Power Dissipation
Ensure that the power loss in the driver and the GaN FETs is maintained below the maximum power dissipation
limit of the package at the operating temperature. The smaller the power loss in the driver and the GaN FETs,
the higher the maximum operating frequency that can be achieved in the application.. The total power dissipation
of the LMG5200 device is the sum of the gate driver losses, the bootstrap diode power loss and the switching
and conduction losses in the FETs.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated using
Equation 2.
( ) ^{P = 2 ´ Q}_g ^{´ V}_DD ^{´ f}_SW
where
• Q_g is the gate charge
• V_DD is the bias supply
• f_SW is the switching frequency
(2)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the outputs.
Figure 1 shows the measured gate driver power dissipation versus frequency and load capacitance. Use this
graph to approximate the power losses due to the gate drivers.
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Higher input
voltages (V_IN) to the half bridge also result in higher reverse recovery losses.
The power losses due to the GaN FETs can be divided into conduction losses and switching losses. Conduction
losses are resistive losses and can be calculated using Equation 3.
( ) ( ) ^PCOND
æ
=ç
I_RMS(HS)
2
´
R_DS(on)HS
ö
÷
+
æ
ç
I_RMS(LS)
2
´
R_DS(on)LS
ö
÷
è
øè
ø
where
• R_DS(on)HS is the high-side GaN FET on-resistance
• R_DS(on)LS is the low-side GaN FET on-resistance
• I_RMS(HS) is the high-side GaN FET RMS current
• I_RMS(LS) and low-side GaN FET RMS current
(3)
The switching losses can be computed to a first order using Equation 4.
P_SW = V_IN ´ I_OUT ´ f_SW ´ t_TR
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