LMG5200_15 Datasheet, PDF (14/23 Pages) Texas Instruments – GaN TECHNOLOGY PREVIEWLMG5200 80-V, GaN Half-Bridge Power Stage

LMG5200
SNOSCY4A – MARCH 2015 – REVISED MARCH 2015
11 Layout
www.ti.com
11.1 Layout Guidelines
To maximize the efficiency benefits of fast switching, its extremely important to optimize the board layout such
that the power loop impedance is minimum. When using a multilayer board (more than 2 layers), power loop
parasitic impedance is minimized by having the return path to the input capacitor (between VIN and PGND) small
and directly underneath the first layer as shown in Figure 12 and Figure 13. Loop inductance is reduced due to
inductance cancellation as the return current is directly underneath and flowing in the opposite direction. It is also
critical that the VCC capacitors and the bootstrap capacitors are as close to the device as possible and in the
first layer. Carefully consider the AGND connection of LMG5200 device. It should NOT be directly connected to
PGND so that PGND noise does not directly shift AGND and cause spurious switching events due to noise
injected in HI and LI signals. Placements shown in Figure 12 and in the cross section of Figure 13 show the
suggested placement of the device with respect to sensitive passive components, such as VIN, bootstrap
capacitors (HS and HB) and VSS capacitors. Use appropriate spacing in the layout to reduce creepage and
maintain clearance requirements in accordance with the application pollution level. Inner layers if present can be
more closely spaced due to negligible pollution.
PGND
Metal underneath solder mask
VIN Capacitors
VIN
HS HB
VIN
HI
LM5200
LI
VCC AGND
PGND
SW
PGND
SW
Legend
Metal 1
Metal 2 (PGND)
Vias
Figure 12. External Component Placement (Single Layer)
14
Submit Documentation Feedback
Product Folder Links: LMG5200
Copyright © 2015, Texas Instruments Incorporated