LM3S608-IQN50-C2T Datasheet, PDF (9/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S608 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S608 Microcontroller High-Level Block Diagram ................................. 33
Figure 2-1. CPU Block Diagram ............................................................................................. 42
Figure 2-2. TPIU Block Diagram ............................................................................................ 43
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 45
Figure 2-4. Bit-Band Mapping ................................................................................................ 65
Figure 2-5. Data Storage ....................................................................................................... 66
Figure 2-6. Vector Table ........................................................................................................ 71
Figure 2-7. Exception Stack Frame ........................................................................................ 73
Figure 3-1. SRD Use Example ............................................................................................... 88
Figure 4-1. JTAG Module Block Diagram .............................................................................. 141
Figure 4-2. Test Access Port State Machine ......................................................................... 144
Figure 4-3. IDCODE Register Format ................................................................................... 148
Figure 4-4. BYPASS Register Format ................................................................................... 149
Figure 4-5. Boundary Scan Register Format ......................................................................... 149
Figure 5-1. Basic RST Configuration .................................................................................... 152
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 152
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 153
Figure 5-4. Main Clock Tree ................................................................................................ 156
Figure 6-1. Flash Block Diagram .......................................................................................... 207
Figure 7-1. GPIO Port Block Diagram ................................................................................... 227
Figure 7-2. GPIODATA Write Example ................................................................................. 228
Figure 7-3. GPIODATA Read Example ................................................................................. 228
Figure 8-1. GPTM Module Block Diagram ............................................................................ 265
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 269
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 270
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 271
Figure 9-1. WDT Module Block Diagram .............................................................................. 301
Figure 10-1. ADC Module Block Diagram ............................................................................... 325
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 329
Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 329
Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 330
Internal Temperature Sensor Characteristic ......................................................... 331
Figure 11-1. UART Module Block Diagram ............................................................................. 361
Figure 11-2. UART Character Frame ..................................................................................... 362
Figure 12-1. SSI Module Block Diagram ................................................................................. 400
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 403
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 404
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 404
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 405
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 406
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 406
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 407
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 408
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 408
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 409
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 410
June 18, 2012
9
Texas Instruments-Production Data