LM3S608-IQN50-C2T Datasheet, PDF (6/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
10.3 Functional Description ................................................................................................. 325
10.3.1 Sample Sequencers .................................................................................................... 326
10.3.2 Module Control ............................................................................................................ 326
10.3.3 Hardware Sample Averaging Circuit ............................................................................. 327
10.3.4 Analog-to-Digital Converter .......................................................................................... 327
10.3.5 Differential Sampling ................................................................................................... 328
10.3.6 Test Modes ................................................................................................................. 330
10.3.7 Internal Temperature Sensor ........................................................................................ 330
10.4 Initialization and Configuration ..................................................................................... 331
10.4.1 Module Initialization ..................................................................................................... 331
10.4.2 Sample Sequencer Configuration ................................................................................. 331
10.5 Register Map .............................................................................................................. 332
10.6 Register Descriptions .................................................................................................. 333
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11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
11.6
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 360
Block Diagram ............................................................................................................ 361
Signal Description ....................................................................................................... 361
Functional Description ................................................................................................. 362
Transmit/Receive Logic ............................................................................................... 362
Baud-Rate Generation ................................................................................................. 362
Data Transmission ...................................................................................................... 363
FIFO Operation ........................................................................................................... 363
Interrupts .................................................................................................................... 364
Loopback Operation .................................................................................................... 365
Initialization and Configuration ..................................................................................... 365
Register Map .............................................................................................................. 366
Register Descriptions .................................................................................................. 367
12 Synchronous Serial Interface (SSI) .................................................................... 400
12.1 Block Diagram ............................................................................................................ 400
12.2 Signal Description ....................................................................................................... 400
12.3 Functional Description ................................................................................................. 401
12.3.1 Bit Rate Generation ..................................................................................................... 401
12.3.2 FIFO Operation ........................................................................................................... 401
12.3.3 Interrupts .................................................................................................................... 402
12.3.4 Frame Formats ........................................................................................................... 402
12.4 Initialization and Configuration ..................................................................................... 410
12.5 Register Map .............................................................................................................. 411
12.6 Register Descriptions .................................................................................................. 412
13 Inter-Integrated Circuit (I²C) Interface ................................................................ 438
13.1 Block Diagram ............................................................................................................ 439
13.2 Signal Description ....................................................................................................... 439
13.3 Functional Description ................................................................................................. 439
13.3.1 I²C Bus Functional Overview ........................................................................................ 440
13.3.2 Available Speed Modes ............................................................................................... 442
13.3.3 Interrupts .................................................................................................................... 443
13.3.4 Loopback Operation .................................................................................................... 443
13.3.5 Command Sequence Flow Charts ................................................................................ 443
13.4 Initialization and Configuration ..................................................................................... 451
13.5 Register Map .............................................................................................................. 452
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June 18, 2012
Texas Instruments-Production Data