LM3S608-IQN50-C2T Datasheet, PDF (18/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 423
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 424
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 425
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 426
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 427
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 428
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 429
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 430
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 431
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 432
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 433
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 434
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 435
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 436
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 437
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 438
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 454
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 455
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 459
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 460
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 461
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 462
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 463
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 464
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 465
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 467
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 468
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 470
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 471
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 472
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 473
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 474
Analog Comparator ..................................................................................................................... 475
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 480
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 481
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 482
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 483
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 484
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 485
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June 18, 2012
Texas Instruments-Production Data