LM3S608-IQN50-C2T Datasheet, PDF (468/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

NRND: Not recommended for new designs.
Inter-Integrated Circuit (I²C) Interface
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x804
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and
receives the first data byte from the I²C master. The Receive Request (RREQ) bit indicates that
the Stellaris I²C device has received a data byte from an I²C master. Read one data byte from the
I²C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris I²C device is addressed as a Slave Transmitter. Write one data byte into
the I²C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I²C slave operation.
Reads
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
Offset 0x804
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FBR TREQ RREQ
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
0
Name
reserved
FBR
TREQ
RREQ
Type
RO
RO
RO
RO
Reset
0x00
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
Transmit Request
This bit specifies the state of the I²C slave with regards to outstanding
transmit requests. If set, the I²C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
Receive Request
This bit specifies the status of the I²C slave with regards to outstanding
receive requests. If set, the I²C unit has outstanding receive data from
the I²C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
468
June 18, 2012
Texas Instruments-Production Data