LM3S608-IQN50-C2T Datasheet, PDF (122/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

Cortex-M3 Peripherals
NRND: Not recommended for new designs.
Register 28: Configurable Fault Status (FAULTSTAT), offset 0xD28
Note: This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
■ Usage Fault Status (UFAULTSTAT), bits 31:16
■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
■ The complete FAULTSTAT register, with a word access to offset 0xD28
■ The MFAULTSTAT, with a byte access to offset 0xD28
■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
■ The BFAULTSTAT, with a byte access to offset 0xD29
■ The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
reserved
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
25
24
23
DIV0 UNALIGN
R/W1C R/W1C RO
0
0
0
15
BFARV
Type R/W1C
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
BSTKE BUSTKE IMPRE PRECISE IBUS MMARV
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
0
0
0
0
0
0
22
21
reserved
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
NOCP INVPC INVSTAT UNDEF
RO R/W1C R/W1C R/W1C R/W1C
0
0
0
0
0
4
3
2
1
0
MSTKE MUSTKE reserved DERR IERR
R/W1C R/W1C RO R/W1C R/W1C
0
0
0
0
0
Bit/Field
31:26
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
122
June 18, 2012
Texas Instruments-Production Data