LM3S608-IQN50-C2T Datasheet, PDF (408/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

NRND: Not recommended for new designs.
Synchronous Serial Interface (SSI)
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
Q MSB
SSITx
MSB
4 to 16 bits
LSB Q
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.3.4.7
MICROWIRE Frame Format
Figure 12-10 on page 408 shows the MICROWIRE frame format, again for a single frame. Figure
12-11 on page 409 shows the same format when back-to-back frames are transmitted.
Figure 12-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSITx
SSIRx
MSB
8-bit control
LSB
0 _MSB
LSB
4 to 16 bits
output data
408
June 18, 2012
Texas Instruments-Production Data