CDC7005RGZT Datasheet, PDF (9/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic
Table 5. Reference Divider M and VCXO Divider N (See Note 4)
M9 M8
M7
M6
M5
M4
M3
M2
M1
M0
DIV BY^{
DEFAULT
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
1
1
4
•
•
•
0
0
0
1
1
1
1
1
1
1
128
Yes
•
•
•
1
1
1
1
1
1
1
1
0
1
1022
1
1
1
1
1
1
1
1
1
0
1023
1
1
1
1
1
1
1
1
1
1
1024
NOTE 4: If the divider value is Q, then the code will be the binary value of (Q−1).
† _{The frequency applied to the Divider N must be smaller than 250 MHz. A sufficient P Divider must be selected with the MUX_SEL to maintain}
this criteria.
Table 6. Reference Delay M and VCXO Delay N
MD2/ND2
MD1/ND1
MD0/ND0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
† _{Typical values at VCC = 3.3 V, temperature = 25°C}
DELAY†
0 ps
150 ps
300 ps
450 ps
600 ps
750 ps
1.5 ns
2.75 ns
Table 7. PFD Pulse Width Delay
PFD2
PFD1
PFD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
† _{Typical values at VCC = 3.3 V, temperature = 25°C}
ADDITIONAL PULSE WIDTH†
0 ps
300 ps
600 ps
900 ps
1.5 ns
2.1 ns
2.7 ns
3.7 ns
DEFAULT
Yes
DEFAULT
Yes
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