CDC7005RGZT Datasheet, PDF (3/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
Pin Functions
NAME
AVCC
CP_OUT
CTRL_LE
CTRL_CLK
CTRL_DATA
GND
I_REF
NC
NPD
PIN
BGA
C3, C4, C5, C6, C7
A4
A1
QFN
27, 30, 32, 38, 39
31
36
TYPE
Power
O
I
A2
35
I
A3
33
I
B2, B3, B4, B5, B6,
B7, B8, C2, D2, D3,
D4, D5, D6, E2, F2,
F3, F4, F5, F6
C1
Thermal pad and
pin 24
40
Ground
O
−
34
−
H1
1
I
DESCRIPTION
3.3-V analog power supply
Charge pump output
LVCMOS input, control load enable for serial programmable
interface (SPI) with hysteresis. Unused or floating inputs must be
tied to proper logic level. It is recommend to use a 20kΩ or larger
pull−up resistor to VCC.
LVCMOS input, serial control clock input for SPI, with hysteresis.
Unused or floating inputs must be tied to proper logic level. It is
recommend to use a 20kΩ or larger pull−up resistor to VCC.
LVCMOS input, serial control data input for SPI, with hysteresis.
Unused or floating inputs must be tied to proper logic level. It is
recommend to use a 20kΩ or larger pull−up resistor to VCC.
Ground
Current path for external reference resistor (12 kΩ ±1%) to support
an accurate charge pump current, optional. Do not use any
capacitor across this resistor to prevent noise coupling via this
node. If internal 12 kΩ is selected (default setting), this pin can be
left open.
Not connected
LVCMOS input, asynchronous power down (PD) signal active on
low. Switches all current sources off, resets all dividers to default
values, and 3-states all outputs. Has an internal 150-kΩ pullup
resistor.
Note 2: It is recommended to ramp up NPD at the same time with
VCC and AVCC or later. The ramp up rate should not be faster than
the ramp up rate of VCC and AVCC
NRESET
H8
OPA_IN
A5
OPA_OUT
A7
OPA_IP
A6
REF_IN
B1
STATUS_LOCK
A8
STATUS_REF
C8
STATUS_VCXO
D8
14
I
LVCMOS input, asynchronous reset signal active on low. Resets
the counter of all dividers to zero keeping its divider values the
same. It has an internal 150-kΩ pullup resistor. Yx outputs are
switched low during reset.
29
I
Inverting input of the op amp, see Note 1
26
O
Output of the op amp, see Note 1
28
I
Noninverting input of the op amp, see Note 1
37
I
LVCMOS reference clock input
25
O
This pin is high if the PLL lock definition is valid. PLL lock definition
means the rising edge of REF_IN clock and VCXO_IN clock for
PFD are inside the lock detect window for at least five successive
input clock cycles. If the rising edge of REF_IN clock and VCXO_IN
clock are out of the selected lock detect window, this pin will be low,
but it does not refer to the real lock condition of the PLL. This
means, that i.e. due to a strong jitter at REF_IN or VCXO_IN
STATUS_LOCK can be low, even if the PLL is in Lock. The PLL is
in lock for sure, if STATUS_LOCK is high.See Table 8 and Figure 4.
23
O
LVCMOS output provides the status of the reference input
(frequencies above 3.5 MHz are interpreted as valid clock, active
high)
22
O
LVCMOS outputs provides the status of the VCXO input
(frequencies above 10 MHz are interpreted as valid clock, active
high)
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