CDC7005RGZT Datasheet, PDF (11/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic (continued)
MUX2
0
0
0
0
1
1
1
1
Table 11. MUX0, MUX1, MUX2, MUX3, and MUX4 Selection
MUX1
0
0
1
1
0
0
1
1
MUX0
0
1
0
1
0
1
0
1
SELECTED DIVIDED VCXO SIGNAL
Div by 1
Div by 2
Div by 4
Div by 8
Div by 16
Div by 8
Div by 8
Div by 8
DEFAULT
For Y0
For Y1
For Y2
For Y3 and Y4
REF_IN Clock Fed Through
the M Divider and Delay
VCXO_IN Clock Fed Through
the N Divider and Delay
V(PFD1) (Internal Signal)
V(PFD2) (Internal Signal)
ICP (Bit 30 of Word 1 = 1,
Default State)
PFD Pulse
Width Delay
0V
PFD Pulse
Width Delay
VCC
ICP (Bit 30 of Word 1 = 0)
NOTE: The purpose of the PFD pulse width delay is to improve spurious suppression. (See Table 7)
Figure 2. Charge Pump Current Direction
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