CDC7005RGZT Datasheet, PDF (1/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
D High Performance 1:5 PLL Clock
Synchronizer
TERMINAL ASSIGNMENTS
(TOP VIEW)
D Two Clock Inputs: VCXO_IN Clock Is
1
2
3
4
5
6
7
8
Synchronized To REF_IN Clock
D Synchronizes Frequencies Up To 800 MHz
A
CTRL_LE
CTRL_
CLK
CTRL_
DATA
CP_OUT
OPA_IN
OPA_IP
OPA_OUT
STATUS_
LOCK
(VCXO_IN)
B REF_IN GND
GND
GND
GND
GND
GND
GND
D Supports Five Differential LVPECL Outputs
D Each Output Frequency Is Selectable By
C I_REF GND
AV_CC
AV_CC
AV_CC
AV_CC
STATUS_
AV_CC
REF
x1, /2, /4, /8, /16
D All Outputs Are Synchronized
D VCXO_IN GND
GND
GND
GND
GND
V_CC
STATUS_
VCXO
D Integrated Low-Noise OPA For External
Low-Pass Filter
E
VCXO_IN
B
GND
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
D Efficient Jitter Screening From Low PLL
Loop Bandwidth
F
Y0
GND
GND
GND
GND
GND
V_CC
Y4B
D Low-Phase Noise Characteristic
D Programmable Delay For Phase
G Y0B
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
Y4
Adjustments
H NPD
Y1
Y1B
Y2
Y2B
Y3
Y3B NRESET
D Predivider Loop BW Adjustment
D SPI Controllable Division Setting
D Power-Up Control Forces LVPECL Outputs
to 3-State at VCC < 1.5 V
D 3.3-V Power Supply
36
25
D Packaged In 64-Pin BGA (0,8 mm Pitch −
ZVA) or 48-Pin QFN (RGZ)
D Industrial Temperature Range –40°C
To 85°C
37
REF_IN
AVCC
AVCC
I_REF
VCC
Top View
24
GND
STATUS_REF
STATUS_VCXO
VCC
VCC
description
The CDC7005 is a high-performance, low-phase
noise, and low-skew clock synthesizer and jitter
cleaner that synchronizes the voltage controlled
crystal oscillator (VCXO) frequency to the
reference clock. The programmable predividers
M and N give a high flexibility to the frequency ratio
VCXO_IN
VCXO_INB
VCC
VCC
Y0
Y0B
VCC
48
1
Thermal Pad
must be
soldered to
GND
VCC
VCC
Y4B
Y4
VCC
NRESET
VCC
13
12
of the reference clock to VCXO: VCXO_IN/
REF_IN = (NxP)/M. The VCXO_IN clock operates
up to 800 MHz. Through the selection of external
VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different
system requirements. Each of the five differential LVPECL outputs are programmable by the serial peripheral
interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The
device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.
The CDC7005 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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