CDC7005RGZT Datasheet, PDF (19/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
application specific device characteristics over recommended operating free-air temperature
range (unless otherwise noted)
PARAMETER
REF_IN
PHASE
NOISE AT
30.72 MHz
VCXO
PHASE
NOISE AT
245.76 MHz
Yn PHASE NOISE AT
30.72 MHz
MIN TYP† MAX
UNIT
phn10
phn100
Phase noise at 10 Hz
Phase noise at 100 Hz
−115
−77
−125
−95
−105
−116
dBc/Hz
dBc/Hz
phn1k Phase noise at 1 kHz
−131
−118
−135
dBc/Hz
phn10k Phase noise at 10 kHz
−136
−136
−147
dBc/Hz
phn100k Phase noise at 100 kHz
−138
−138
−152
dBc/Hz
phn240k Phase noise at 240 kHz
−140
−143
−152
dBc/Hz
tstabi
PLL stabilization time, (see Note 15)
† _{Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor.}
200
ms
NOTES: 15. The typical stabilization time is based on the above application example at a loop bandwidth of 20 Hz.
16. For further explanations as well as phase noise/jitter test results using various VCXOs, see application note SCAA067.
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