CDC7005RGZT Datasheet, PDF (10/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic (continued)
Table 8. Lock Detect Window
LockW 1
LockW 0
REF_IN TO Yn TOLERABLE PHASE OFFSET (See Figure 4 and Note 1)
0
0
±1.2 ns
0
1
±1.8 ns
1
0
±2.4 ns
1
1
±3 ns
NOTE 1: Determined at PFD − REF_IN and Yn feed through M/N Divider and M/N Delay.
Table 9. Charge Pump Current
CP3
CP2
CP1
CP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
† _{With an internal or external reference resistor (12 kΩ) in use.}
NOMINAL CHARGE PUMP CURRENT†
0.625 mA
1.25 mA
1.875 mA
2.5 mA
3.125 mA
3.75 mA
4.375 mA
5 mA
1 mA
2 mA
3 mA
4 mA
5 mA
6 mA
7 mA
8 mA
MUXS2
0
0
0
0
1
1
1
1
MUXS1
0
0
1
1
0
0
1
1
Table 10. MUXSEL Selection
MUXS0
0
1
0
1
0
1
0
1
SELECTED VCXO SIGNAL FOR THE PHASE
DISCRIMINATOR
Y0
Y1
Y2
Y3
Y4
Y3
Y3
Y3
DEFAULT
Yes
DEFAULT
Yes
DEFAULT
Yes
10
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