CDC7005RGZT Datasheet, PDF (14/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
timing requirements over recommended ranges of supply voltage, load, and operating free-air
temperature
PARAMETER
REF_IN Requirements
fREF_IN
LVCMOS reference clock frequency
tr / tf
Rise and fall time of REF_IN signal from 20% to 80% of VCC
dutyREF
Duty cycle of REF_IN at VCC / 2
VCXO_IN, VCXO_INB Requirements
fVCXO_IN LVPECL VCXO clock frequency
tr / tf
Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz (see Note 8)
dutyVCXO Duty cycle of VCXO clock
SPI/Control Requirements (See Figure 1)
fCTRL_CLK CTRL_CLK frequency
tsu1
CTRL_DATA to CTRL_CLK setup time
th2
CTRL_DATA to CTRL_CLK hold time
t3
CTRL_CLK high duration
t4
CTRL_CLK low duration
tsu5
CTRL_LE to CTRL_CLK setup time
tsu6
CTRL_CLK to CTRL_LE setup time
t7
CTRL_LE pulse width
tr / tf
Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC
NPD / NRESET Requirements
tr / tf
Rise and fall time of the NRESET, NPD signal from 20% to 80% of VCC
NOTES: 8. Use a square wave for lower frequencies (< 80 MHz).
MIN TYP MAX UNIT
3.5
40%
180
4
60%
MHz
ns
10
40%
800
3
60%
MHz
ns
20 MHz
10
ns
10
ns
25
ns
25
ns
10
ns
10
ns
20
ns
5 ns
4 ns
14
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