CDC7005RGZT Datasheet, PDF (20/34 Pages) Texas Instruments – 3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER

CDC7005
3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
APPLICATION INFORMATION
information on the clock generation for interpolating DACs with the CDC7005
The CDC7005, with its specified phase noise performance, is an ideal sampling clock generator for high speed
ADCs and DACs. The CDC7005 is especially of interest for the new high speed DACs, which have integrated
interpolation filter. Such DACs achieve sampling rates up to 500 MSPS. This high data rate can typically not
be supported from the digital side driving the DAC (e.g., DUC, digital up-converter). Therefore, one approach
to interface the DUC to the DAC is the integration of an interpolation filter within the DAC to reduce the data rate
at the digital input of the DAC. In 3G systems, for example, a common sampling rate of a high speed DAC is
245.76 MSPS. With a four times interpolation of the digital data, the required input data rate results into
61.44 MSPS, which can be supported easily from the digital side. The DUC GC4116, which supports up to two
WCDMA carriers, provides a maximum output data rate of 100 MSPS. An example is shown in Figure 8, where
the CDC7005 supplies the clock signal for the DUC/DDC and ADC/DAC.
GC4016
I
THS4502
To BB
DDC
12-Bit
ADC
Q
IF2
LNA
IF1
RF
Duplexer
3.84 MHz
VCXO
245.76 MHz
61.44 MHz
CDC7005
61.44 MHz 61.44 MHz
245.76 MHz
LO1
(PLL)
I
FIR
FIR
16-Bit
DAC
From BB
DUC
PA
Σ
Q
FIR
FIR
GC4116 _DAC5686
16-Bit
DAC
0
90
LO1
(PLL)
Figure 8. CDC7005 as a Clock Generator for High Speed ADCs and DACs
The generation of the two required clock signals (data input clock, clock for DAC) for such an interpolating DAC
can be done in different ways. The easiest way would be to provide an internal PLL multiplier, which is capable
of generating the fast sampling clock for the DAC from the data input clock signal. However, the process of the
DAC is usually not optimized for best phase noise performance, while the CDC7005 is optimized exactly for this.
The CDC7005 therefore provides the preferred clocking scheme for the DAC5686. The DAC5686 demands that
the edges of the two input clocks must be phase aligned within ±500 ps for latching the data properly. This phase
alignment is well achieved with the CDC7005, which assures a maximum skew of 200 ps of the different different
outputs to each other.
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