AM1806_1005 Datasheet, PDF (84/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
LPSC
Number
0
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Module Name
Table 6-10. PSC1 Default Module Configuration
Power Domain
Default Module State
EDMA3 Channel Controller 1
USB0 (USB2.0)
—
GPIO
UHPI
—
DDR2 (and SCR_F3)
McASP0 ( + McASP0 FIFO)
SATA
—
VPIF
SPI 1
I2C 1
UART 1
UART 2
McBSP0 ( + McBSP0 FIFO)
McBSP1 ( + McBSP1 FIFO)
LCDC
eHRPWM0/1
MMCSD1
uPP
ECAP0/1/2
EDMA3 Transfer Controller 2
—
—
SCR_F0 (and bridge F0)
SCR_F1 (and bridge F1)
SCR_F2 (and bridge F2)
SCR_F6 (and bridge F3)
SCR_F7 (and bridge F4)
SCR_F8 (and bridge F5)
Bridge F7 (DDR Controller path)
On-chip RAM (including SCR_F4
and bridge F6)
AlwaysON (PD0)
AlwaysON (PD0)
—
AlwaysON (PD0)
AlwaysON (PD0)
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
PD_SHRAM
SwRstDisable
SwRstDisable
—
SwRstDisable
SwRstDisable
—
SwRstDisable
SwRstDisable
SwRstDisable
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
www.ti.com
Auto Sleep/Wake Only
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
84
Peripheral Information and Electrical Specifications
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