AM1806_1005 Datasheet, PDF (47/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
3.7.22 Video Port Interface (VPIF)
Table 3-24. Video Port Interface (VPIF) Terminal Functions
SIGNAL
NAME
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] /
UPP_2xTXCLK
TYPE ⁽¹⁾
NO.
VIDEO INPUT
W14
I
VP_CLKIN1 / UHPI_HDS1/PRU1_R30[9] / GP6[6] / PRU1_R31[16] V15
I
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /
PRU0_R31[15]
V18
I
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /
PRU0_R31[14]
V19
I
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
PRU0_R31[13]
U19
I
VP_DIN[12] / UHPI_HD[4] / UPP_D[4]/ PRU0_R30[12] /
PRU0_R31[12]
T16
I
VP_DIN[11] / UHPI_HD[3] / UPP_D[3]/ PRU0_R30[11] /
PRU0_R31[11]
R18
I
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
PRU0_R31[10]
R19
I
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] /
PRU0_R31[9]
R15
I
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
P17
I
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / PRU0_R31[29]
U18
I
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / PRU0_R31[28]
V16
I
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / PRU0_R31[27]
R14
I
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / PRU0_R31[26]
W16
I
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / PRU0_R31[25]
V17
I
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / PRU0_R31[24]
W17
I
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / PRU0_R31[23]
W18
I
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / PRU1_R31[29]
W19
I
VIDEO OUTPUT
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
H3
I
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
K3
O
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
J3
I
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]
K4
O
PULL ⁽²⁾
CP[25]
CP[25]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[30]
CP[30]
CP[30]
CP[30]
POWER
GROUP ⁽³⁾
DESCRIPTION
C
VPIF capture channel 0
input clock
C
VPIF capture channel 1
input clock
C
C
C
C
C
C
VPIF capture data bus
C
C
C
C
C
C
C
C
C
C
C
VPIF display channel 2
input clock
C
VPIF display channel 2
output clock
C
VPIF display channel 3
input clock
C
VPIF display channel 3
output clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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