AM1806_1005 Datasheet, PDF (143/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
www.ti.com
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
6.16.2 SPI Electrical Data/Timing
6.16.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-35
through Figure 6-38).
Table 6-61. General Timing Requirements for SPI0 Master Modes⁽¹⁾
NO.
PARAMETER
1 t_c(SPC)M
Cycle Time, SPI0_CLK, All Master
Modes
2 t_w(SPCH)M
Pulse Width High, SPI0_CLK, All
Master Modes
3 t_w(SPCL)M
Pulse Width Low, SPI0_CLK, All
Master Modes
Delay, Polarity = 0, Phase = 0,
initial
to SPI0_CLK rising
4
t_{d(SIMO_SPC)M}
data bit
valid on
SPI0_SI
MO after
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
initial
to SPI0_CLK falling
edge on
SPI0_CL ^{Polarity = 1, Phase = 1,}
K ⁽³⁾
to SPI0_CLK falling
Delay, Polarity = 0, Phase = 0,
subsequ from SPI0_CLK rising
5
t_{d(SPC_SIMO)M}
ent bits
valid on
SPI0_SI
MO after
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
transmit from SPI0_CLK falling
edge of
SPI0_CL ^{Polarity = 1, Phase = 1,}
K
from SPI0_CLK rising
Output Polarity = 0, Phase = 0,
hold
from SPI0_CLK falling
6
t_{oh(SPC_SIMO)M}
time,
SPI0_SI
MO valid
after
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
receive from SPI0_CLK rising
edge of
SPI0_CL ^{Polarity = 1, Phase = 1,}
K
from SPI0_CLK falling
Input
Polarity = 0, Phase = 0,
Setup to SPI0_CLK falling
Time,
SPI0_S
OMI
Polarity = 0, Phase = 1,
to SPI0_CLK rising
7 t_{su(SOMI_SPC)M} valid
before
Polarity = 1, Phase = 0,
to SPI0_CLK rising
receive
edge of _{Polarity = 1, Phase = 1,}
SPI0_CL _{to SPI0_CLK falling}
K
1.3V, 1.2V
MIN
MAX
20 ⁽²⁾
256P
1.1V
MIN
MAX
30 ⁽²⁾
256P
1.0V
MIN
MAX
40 ⁽²⁾
256P
UNIT
ns
0.5M-1
0.5M-1
0.5M-1
ns
0.5M-1
0.5M-1
0.5M-1
ns
5
5
6
-0.5M+5
5
-0.5M+5
5
-0.5M+6
ns
6
-0.5M+5
-0.5M+5
-0.5M+6
5
5
6
5
5
6
ns
5
5
6
5
5
6
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
ns
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
1.5
1.5
1.5
(1) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 143
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