AM1806_1005 Datasheet, PDF (76/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
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System Interrupt
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
43
44
45
46
Table 6-6. AINTC System Interrupt Assignments
Interrupt Name
COMMTX
COMMRX
NINT
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
EDMA3_0_CC0_INT0
EDMA3_0_CC0_ERRINT
EDMA3_0_TC0_ERRINT
EMIFA_INT
IIC0_INT
MMCSD0_INT0
MMCSD0_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
-
PROTERR
-
-
-
-
EDMA3_0_TC1_ERRINT
-
-
-
-
-
-
-
DDR2_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
Source
ARM
ARM
ARM
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
EDMA3_0 Channel Controller 0 Error Interrupt
EDMA3_0 Transfer Controller 0 Error Interrupt
EMIFA
I2C0
MMCSD0 MMC/SD Interrupt
MMCSD0 SDIO Interrupt
PSC0
RTC
SPI0
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
Reserved
SYSCFG Protection Shared Interrupt
Reserved
Reserved
Reserved
Reserved
EDMA3_0 Transfer Controller 1 Error Interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DDR2 Controller
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
76
Peripheral Information and Electrical Specifications
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