AM1806_1005 Datasheet, PDF (106/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
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6.11.3.2 Compatible JEDEC DDR2/mDDR Devices
Table 6-25 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this
interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade
DDR2/mDDR devices.
The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one
chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control
signals are shared just like regular dual chip memory configurations.
Table 6-25. Compatible JEDEC DDR2/mDDR Devices
No. Parameter
1 JEDEC DDR2/mDDR Device Speed Grade
Min
Max
DDR2/mDDR-400
Unit
Notes
See Note ⁽¹⁾
2 JEDEC DDR2/mDDR Device Bit Width
3 JEDEC DDR2/mDDR Device Count
x8
x16
Bits
1
2
Devices See Note ⁽²⁾
(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.
(2) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories
6.11.3.3 PCB Stackup
The minimum stackup required for routing the device is a six layer stack as shown in Table 6-26.
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size
of the PCB footprint.Complete stack up specifications are provided in Table 6-27.
Layer
1
2
3
4
5
6
Table 6-26. Device Minimum PCB Stack Up
Type
Signal
Plane
Plane
Signal
Plane
Signal
Description
Top Routing Mostly Horizontal
Ground
Power
Internal Routing
Ground
Bottom Routing Mostly Vertical
Table 6-27. PCB Stack Up Specifications
No. Parameter
1 PCB Routing/Plane Layers
2 Signal Routing Layers
3 Full ground layers under DDR2/mDDR routing region
4 Number of ground plane cuts allowed within DDR routing region
5 Number of ground reference planes required for each DDR2/mDDR routing layer
6 Number of layers between DDR2/mDDR routing layer and reference ground plane
7 PCB Routing Feature Size
8 PCB Trace Width w
8 PCB BGA escape via pad size
9 PCB BGA escape via hole size
10 Device BGA pad size
11 DDR2/mDDR Device BGA pad size
12 Single Ended Impedance, Zo
13 Impedance Control
Min Typ Max
6
3
2
0
1
0
4
4
18
8
50
75
Z-5 Z Z+5
(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.
(2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
Unit Notes
Mils
Mils
Mils
Mils
See Note ⁽¹⁾
See Note ⁽²⁾
Ω
Ω See Note ⁽³⁾
106 Peripheral Information and Electrical Specifications
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