AM1806_1005 Datasheet, PDF (83/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
www.ti.com
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
Table 6-8. Power and Sleep Controller (PSC) Registers (continued)
PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS
ACRONYM
-
0x01E2 7A74
MDCTL29
-
0x01E2 7A78
MDCTL30
-
0x01E2 7A7C
MDCTL31
REGISTER DESCRIPTION
Module 29 Control Register
Module 30 Control Register
Module 31 Control Register
6.8.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-9 and Table 6-10 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.8.1.1.
LPSC
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Module Name
Table 6-9. PSC0 Default Module Configuration
Power Domain
Default Module State
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
EMIFA (Br7)
SPI 0
MMC/SD 0
ARM Interrupt Controller
ARM RAM/ROM
—
UART 0
SCR0 (Br 0, Br 1, Br 2, Br 8)
SCR1 (Br 4)
SCR2 (Br 3, Br 5, Br 6)
PRUSS
ARM
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
—
SwRstDisable
Enable
Enable
Enable
SwRstDisable
SwRstDisable
—
Auto Sleep/Wake Only
—
—
—
—
—
—
—
Yes
—
—
Yes
Yes
Yes
—
—
—
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
83
Submit Documentation Feedback
Product Folder Link(s): AM1806