AM1806_1005 Datasheet, PDF (147/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
Table 6-64. Additional SPI0 Master Timings, 4-Pin Chip Select Option ^{(1) (2) (3)} (continued)
NO.
PARAMETER
20 t_{d(SPC_SCS)M}
Delay from final SPI0_CLK edge to master deasserting
SPI0_SCS ^{(6) (7)}
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
1.3V, 1.2V
MIN
MAX
0.5M+P-1
1.1V
MIN
MAX
0.5M+P-2
P-1
P-2
0.5M+P-1
0.5M+P-2
P-1
P-2
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
1.0V
UNIT
MIN
MAX
0.5M+P-3
P-3
ns
0.5M+P-3
P-3
Table 6-65. Additional SPI0 Master Timings, 5-Pin Option ^{(1) (2) (3)}
NO.
PARAMETER
Polarity = 0, Phase = 0,
from SPI0_CLK falling
18 t_{d(SPC_ENA)M}
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer.⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
20 t_{d(SPC_SCS)M}
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS ^{(5) (6)}
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid after master
21 t_{d(SCSL_ENAL)M} asserts SPI0_SCS to delay the master from beginning the next
transfer,
1.3V, 1.2V
MIN
MAX
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P-2
P-2
0.5M+P-2
P-2
C2TDELAY+P
1.1V
MIN
MAX
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P-2
P-2
0.5M+P-2
P-2
C2TDELAY+P
1.0V
MIN
MAX
0.5M+P+6
P+6
0.5M+P+6
P+6
0.5M+P-3
P-3
0.5M+P-3
P-3
UNIT
ns
ns
C2TDELAY+P ns
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-62 ).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Peripheral Information and Electrical Specifications 147