AM1806_1005 Datasheet, PDF (112/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
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6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
A1
T
A
A1
Figure 6-21. CK and ADDR_CTRL Routing and Topology
Table 6-34. CK and ADDR_CTRL Routing Specification
No. Parameter
1 Center to Center CK-CKN Spacing
2 CK A to B/A to C Skew Length Mismatch
3 CK B to C Skew Length Mismatch
4 Center to center CK to other DDR2/mDDR trace spacing
5 CK/ADDR_CTRL nominal trace length
6 ADDR_CTRL to CK Skew Length Mismatch
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
8 Center to center ADDR_CTRL to other DDR2/mDDR trace spacing
9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing
10 ADDR_CTRL A to B/A to C Skew Length Mismatch
11 ADDR_CTRL B to C Skew Length Mismatch
Min
4w ⁽¹⁾
CACLM-50
4w ⁽¹⁾
3w ⁽¹⁾
Typ
CACLM
Max
Unit
Notes
2w ⁽¹⁾
25
See Note ⁽²⁾
Mils See Note ⁽³⁾
25
Mils
See Note ⁽²⁾
CACLM+50 Mils See Note ⁽⁴⁾
100
Mils
100
Mils
See Note ⁽²⁾
See Note ⁽²⁾
100
Mils See Note ⁽³⁾
100
Mils
(1) w = PCB trace width as defined in Table 6-27 .
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) Series terminator, if used, should be located closest to device.
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
112 Peripheral Information and Electrical Specifications
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