AM1806_1005 Datasheet, PDF (61/241 Pages) Texas Instruments – AM1806 ARM Microprocessor

AM1806
www.ti.com
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
5.2 Recommended Operating Conditions
Supply
Voltage
Supply
Ground
Voltage
Input High
Voltage
Input Low
USB
Transition
Time
NAME
CVDD
RVDD
RTC_CVDD ⁽¹⁾
PLL0_VDDA
PLL1_VDDA
USB_CVDD
USB0_VDDA18
USB0_VDDA33
DDR_DVDD18
DDR_VREF
DDR_ZP
DVDD3318_A
DVDD3318_B
DVDD3318_C
DESCRIPTION
CONDITION
Core Logic Supply Voltage (variable) 1.3V operating point
1.2V operating point
1.1V operating point
1.0V operating point
Internal RAM Supply Voltage
RTC Core Logic Supply Voltage
PLL0 Supply Voltage
PLL1 Supply Voltage
USB0 Core Logic Supply Voltage
USB0 PHY Supply Voltage
USB0 PHY Supply Voltage
DDR2 PHY Supply Voltage
DDR2/mDDR reference voltage
DDR2/mDDR impedance control,
connected via 50Ω resistor to Vss
Power Group A Dual-voltage IO
Supply Voltage
Power Group B Dual-voltage IO
Supply Voltage
Power Group C Dual-voltage IO
Supply Voltage
1.8V operating point
3.3V operating point
1.8V operating point
3.3V operating point
1.8V operating point
3.3V operating point
MIN
1.25
1.14
1.05
0.95
1.14
0.9
1.14
1.14
1.14
1.71
3.15
1.71
0.49*
DDR_DVDD18
1.71
3.15
1.71
3.15
1.71
3.15
NOM
1.3
1.2 or 1.26
1.1
1.0
1.2 or 1.26
1.2 or 1.26
1.2 or 1.26
1.2 or 1.26
1.2 or 1.26
1.8
3.3
1.8
0.5*
DDR_DVDD1
8
Vss
1.8
3.3
1.8
3.3
1.8
3.3
MAX
1.35
1.32
1.16
1.05
1.32
1.32
1.32
1.32
1.32
1.89
3.45
1.89
0.51*
DDR_DVDD18
1.89
3.45
1.89
3.45
1.89
3.45
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VSS
Core Logic Digital Ground
V
PLL0_VSSA
PLL1_VSSA
OSCVSS ⁽²⁾
RTC_VSS ⁽²⁾
USB0_VSSA
USB0_VSSA33
PLL0 Ground
PLL1 Ground
Oscillator Ground
RTC Oscillator Ground
USB0 PHY Ground
USB0 PHY Ground
V
V
0
0
0
V
V
V
V
V_IH
V_IL
USB0_VBUS
t_t
High-level input voltage, Dual-voltage I/O, 3.3V⁽³⁾
High-level input voltage, Dual-voltage I/O, 1.8V ⁽³⁾
High-level input voltage, RTC_XI
High-level input voltage, OSCIN
Low-level input voltage, Dual-voltage I/O, 3.3V⁽³⁾
Low-level input voltage, Dual-voltage I/O, 1.8V ⁽³⁾
Low-level input voltage, RTC_XI
Low-level input voltage, OSCIN
USB external charge pump input
Transition time, 10%-90%, All Inputs (unless otherwise
specified in the electrical data sections)
2
0.65*DVDD
0.8*RTC_CVDD
0.8*CVDD
0
V
V
V
V
0.8
V
0.35*DVDD
V
0.2*RTC_CVDD V
0.2*CVDD
V
5.25
V
0.25P ⁽⁴⁾
ns
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(2) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(3) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and
adhere to the JESD79-2A standard.
(4) Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity
on input signals.
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Device Operating Conditions
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