CC2520_11 Datasheet, PDF (83/133 Pages) Texas Instruments – 2.4 GHZ IEEE 802.15.4/ZIGBEE RF TRANSCEIVER

CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
• The number of valid bytes in the RX FIFO exceeds the FIFOP threshold value programmed into
FIFOPCTRL. When frame filtering is enabled, the bytes in the frame header are not considered
as valid until the frame has been accepted.
• The last byte of a new frame is received, even if the FIFOP threshold is not exceeded. If so,
FIFOP will go back low at the next RX FIFO read access.
Received frame
Preamble SFD LEN
MPDU (LEN[6:0] bytes)
SFD
FIFO
FIFOP (low threshold)
FIFOP (high threshold)
SFD
FIFO
FIFOP
First byte
received
Frame
filtering
complete
Figure 29: Behavior of FIFO and FIFOP signals.
Last byte
received
When using the FIFOP signal as an interrupt signal for the microcontroller, the FIFOP threshold should be
adjusted by the interrupt service routine to prepare for the next interrupt. When preparing for the last
interrupt for a frame, the threshold should match the number of bytes remaining.
20.4.2 Error Conditions
There are two error conditions associated with the RX FIFO:
• Overflow, in which case the RX FIFO is full when another byte is received
• Underflow, in which case software attempts to read a byte from an empty RX FIFO
RX overflow is indicated by the RX_OVERFLOW exception and by the signal values FIFO = 0 and FIFOP =
1. When the error occurs, frame reception will be halted. The frames currently stored in the RX FIFO may be
read out before the condition is cleared with the SFLUSHRX strobe. Note that rejected frames can generate
RX overflow if the condition occurs before the frame is rejected.
RX underflow is indicated by the RX_UNDERFLOW exception. RX underflow is a serious error condition
that should not occur in error-free software, and the RX_UNDERFLOW exception should only be used for
debugging or in a "watchdog" function. Note that the RX_UNDERFLOW exception will not be generated
when the read operation occurs simultaneously with reception of a new byte.
20.5 RSSI
CC2520 has a built-in RSSI (Received Signal Strength Indication) which calculates an 8 bit signed digital
value that can be read from a register or automatically appended to received frames. The RSSI value is the
result of averaging the received power over 8 symbol periods (128 µs) as specified by IEEE 802.15.4 [2].
The RSSI value is a 2’s complement signed number on a logarithmic scale with 1dB steps.
The statusbit RSSI_VALID should be checked before reading the RSSI value register. RSSI_VALID
indicates that the RSSI value in the register is in fact valid, which means that the receiver has been enabled
for at least 8 symbol periods.
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