CC2520_11 Datasheet, PDF (33/133 Pages) Texas Instruments – 2.4 GHZ IEEE 802.15.4/ZIGBEE RF TRANSCEIVER

CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
10 Serial Peripheral Interface (SPI)
The SPI provides an interface for giving instructions to the CC2520 and transferring data between CC2520
and a microcontroller. The CC2520 4-wire slave interface consists of three input signals (CSn, SCLK and SI)
and one output signal (SO).
In section 15 all instructions available via the SPI interface are listed and described. The instructions are
byte oriented and required bytes sent over the interface to CC2520 vary from 1 and up. To transfer one byte
CSn must be pulled low and SCLK must complete 8 periods starting with a positive edge. There are no
requirements to maximum period for SCLK or that it needs to be continuous. As long as CSn is held low,
SCLK can be halted at any time and started again when desired.
10.1 CSn
CSn is an input enable signal for the SPI and is controlled by the external MCU. The CSn signal is used as
an asynchronous active high reset to the SPI module.
CSn must be held low during all SPI operations and must also be held low for more than two periods of
XOSC before the first positive edge of SCLK and more than two periods of XOSC after the last negative
edge of SCLK.
When CSn is high it must be held high for at least 2 periods of XOSC.
CSn can be held low between SPI operations in the case where the last instruction completed has a
constant number of bytes, but this will result in unnecessary power consumption since parts of the
instruction controller will then be running.
The instructions that have a constant number of bytes can be found in the instruction summary table in
section 15.3. I.e. SRXON (1 byte) and RXMASKAND (3 bytes) has constant number of bytes and REGRD
(2 bytes or more) has user controlled number of bytes indicated in the table by three dots (…) in the byte
column after the last required byte of the instruction command (Byte 3 for REGRD).
Instructions that have user controlled number of bytes are ended by rising CSn.
Status is output as the first byte on SO during the first byte of all instructions. When instructions are
transferred consecutively without rising CSn between them, the status byte on SO may not contain the
correct current status. However, the status will be updated for the second byte of an instruction so i.e
RXMASKAND which outputs status also during the second instruction byte will then output the correct status
during the second byte.
When pulling CSn low after power-up, SO outputs the internal XOSC stable signal combinatorically, so no
edge on SCLK is necessary to find the XOSC stable status. In any case where CSn is pulled low and SO is
low it means that XOSC is still not stable and thus there is no clock in the digital part. The maximum time
from power up to XOSC should be stable is described in section 5.3.
10.2 SCLK
SCLK is controlled by an external MCU and is an input clock to CC2520. SCLK is asynchronous to the
internal XOSC clock in CC2520. The maximum SCLK frequency is 8 MHz. There is no minimum frequency
requirement.
10.3 SI
SI is the serial data input from the microcontroller to CC2520. Data shall be sent with MSB first (bit 7 in each
byte of instruction commands).
Data should be set up on the negative edge of SCLK and will be clocked into CC2520 by the next positive
edge of SCLK.
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