CC2520_11 Datasheet, PDF (38/133 Pages) Texas Instruments – 2.4 GHZ IEEE 802.15.4/ZIGBEE RF TRANSCEIVER

CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
CTRLn
(hex)
0x22
IN
(Command strobes)
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
...
0x43
0x44
...
0x5E
0x5F
OUT
Description of OUT signal
Exception channel B
Complementary exception
channel A
Complementary exception
channel B
Predefined exception channel
for RX related errors.
Predefined exception channel
for general error conditions.
fifo
fifop
cca
sfd
lock
rssi_valid
sampled_cca
rand_i
rand_q
rand_xor_ i_q
sniff_clk
sniff_data
mod_serial_clk
mod_serial_data
Reserved
rx_active
tx_active
Reserved
dpu_core_activepri(0)
dpu_core_activepri(1)
Pin is high when one or more of the exception flags in collection B
are active. It is configurable which exceptions to include in
collection B.
Pin is high when one or more exception flags not in collection A
are active.
Pin is high when one or more exception flags not in collection B
are active.
Predefined exception channel. High when one or more of the
following exception flags are active: RX_UNDERFLOW,
RX_OVERFLOW, RX_FRM_ABORTED and
RXBUFMOV_TIMEOUT
High when one or more of the following exception flags are active:
MEMADDR_ERROR, USAGE_ERROR, OPERAND_ERROR and
SPI_ERROR.
Pin is high when one or more bytes are in the RXFIFO. Low
during RXFIFO overflow.
Pin is high when the number of bytes in the RXFIFO exceeds the
programmable threshold or at least one complete frame is in the
RXFIFO. Also high during RXFIFO overflow. Not to be confused
with the FIFOP exception.
Clear channel assessment. See FSMSTAT1 register for details on
how to configure the behavior of this signal.
Pin is high when a SFD has been received or transmitted. Cleared
when leaving RX/TX respectively. Not to be confused with the
SFD exception.
Pin is high when frequency synthesizer is in lock.
Pin is high when the RSSI value has been updated at least once
since RX was started. Cleared when leaving RX.
A sampled version of the CCA bit from demodulator. The value is
updated whenever a SSAMPLECCA or STXONCCA strobe is
issued.
Random data output from the I channel of the receiver. Updated
at 8MHz.
Random data output from the Q channel of the receiver. Updated
at 8MHz
XOR between I and Q random outputs. Updated at 8MHz
250kHz clock for packet sniffer data.
Data from packet sniffer. Sample data on rising edges of sniff_clk.
250kHz serial data clock from modulator.
Serial data from modulator. Sample data on rising edges of
mod_serial_clk.
Indicates that FFCTRL is in one of the RX states. Active high.
Note: This signal might have glitches, because it has no output
flip-flop and is based on the current state register of the FFCTRL
FSM.
Indicates that FFCTRL is in one of the TX states. Active high.
Note: This signal might have glitches, because it has no output
flip-flop and is based on the current state register of the FFCTRL
FSM.
High when the DPU is busy processing a low priority thread.
High when the DPU is busy processing a high priority thread.
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