CC2520_11 Datasheet, PDF (27/133 Pages) Texas Instruments – 2.4 GHZ IEEE 802.15.4/ZIGBEE RF TRANSCEIVER

CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
The microcontroller will typically be connected to one or more of the GPIO pins. The function of each pin is
independently controlled by the IO module based on register settings. It is possible to observe a large
number of internal signals on the GPIO pins. The GPIO pins can also be configured as inputs and used to
trigger the execution of certain instructions. This would typically be used when the microcontroller needs to
precisely control the timing of an instruction.
The RAM module contains memory which is used for receive and transmit FIFOs (in fixed address ranges)
and temporary storage for other data. There are separate instructions for general memory access and FIFO
access.
The data processing unit (DPU) is responsible for execution of the more advanced instructions. The DPU
includes an AES core, which is used while executing the security instructions. Memory management
(copying, incrementing etc.) is also performed by the DPU.
The Clock/Reset module generates the internal clocks and reset signals.
The RF core contains several submodules that support and control the analog radio modules.
The FSM submodule controls the RF transceiver state, the transmitter and receiver FIFOs and most of the
dynamically controlled analog signals such as power up / down of analog modules. The FSM is used to
provide the correct sequencing of events (such as performing an FS calibration before enabling the
receiver). Also, it provides step by step processing of incoming frames from the demodulator: reading the
frame length, counting the number of bytes received, checks the FCS, and finally, optionally handles
automatic transmission of ACK frames after successful frame reception. It performs similar tasks in TX
including performing an optional CCA before transmission and automatically going to RX after the end of
transmission to receive an ACK frame. Finally, the FSM controls the transfer of data between
modulator/demodulator and the TXFIFO/RXFIFO in RAM.
The modulator transforms raw data into I/Q signals to the transmitter DAC. This is done in compliance with
the IEEE 802.15.4 standard.
The demodulator is responsible for retrieving the sent data from the received signal.
The amplitude information from the demodulator is used by the automatic gain control (AGC). The AGC
adjusts the gain of the analog LNA so that the signal level within the receiver is approximately constant..
The frame filtering and source matching supports the FSM in RF_core by performing all operations
needed in order to do frame filtering and source address matching, as defined by IEEE 802.15.4.
The xosc module interfaces the crystal which is connected to the XOSC32M_Q1 and XOSC32M_Q2 pins.
The xosc module generates a clock for the digital part and RF system, and implements the programmable
crystal frequency tuning.
The BIAS module generates voltage and current references. It relies on a high precision (1%) 56kΩ external
resistor which is shown in the application circuit in Figure 3.
The TX DACs convert the digital baseband signal to analog signals.
After LPF the signal is fed to the TXMIX module, which is an up-converting complex mixer.
The PA amplifies the RF signal up to a maximum of ~5dBm during TX.
The LNA amplifies the received RF signal. The gain is controlled by the digital AGC module so that optimum
sensitivity and interferer rejection is achieved.
The RXMIX module is a complex down-mixer that converts the RF signal to a baseband signal.
A passive anti-aliasing filter (AAF) low pass filters the signal after down mixing.
The low pass filtered I and Q signals and digitized by the ADC.
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