CC2520_11 Datasheet, PDF (47/133 Pages) Texas Instruments – 2.4 GHZ IEEE 802.15.4/ZIGBEE RF TRANSCEIVER

OPCODE
TXBUFCP
MEMCP
MEMCPR
MEMXCP
Inputs Outputs
p
s[7:0]
a[11:0] c[7:0]
c[7:0]
p
c[7:0]
a[11:0]
e[11:0]
s[7:0]
p
c[7:0]
a[11:0]
e[11:0]
s[7:0]
p
c[7:0]
a[11:0]
e[11:0]
s[7:0]
CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
Description
Copy C bytes of data starting from the memory location
starting at address A to the end of TXBUF.
T
T
The SPI interface will output the number of bytes, C, in
TXBUF.
The priority of the instruction is defined by P, which is
either low (if P=0) or high (if P=1).
If TXBUF fills before the operation is completed a
TX_OVERFLOW exception is raised. The remaining
bytes to be moved is available in status register.
A DPU_DONE_L or DPU_DONE_H exception is raised
when the operation completes, depending on the priority
of the instruction. This happens regardless of whether
the operation was successful or not.
A USAGE_ERROR exception is raised if an instruction is
already active with the requested priority level (high or
low).
Copy data from one memory block to another. Copies
the block of C bytes of data from the memory location
starting at address A to the memory location starting at
address E.
The priority of the instruction is defined by P, which is
either low (if P=0) or high (if P=1).
A DPU_DONE_L or DPU_DONE_H exception is raised
when the operation completes, depending on the priority
of the instruction. This happens regardless of whether
the operation was successful or not.
A USAGE_ERROR exception is raised if an instruction is
already active with the requested priority level (high or
low).
Copy data from one memory block to another, and revert
endianess. Copies the block of C bytes of data from the
memory location starting at address A to the memory
location starting at address E, while reverting the
endianess of the data block. I.e., data from memory
location (A+n) is written to memory location (E+C-1-n).
The priority of the instruction is defined by P, which is
either low (if P=0) or high (if P=1).
A DPU_DONE_L or DPU_DONE_H exception is raised
when the operation completes, depending on the priority
of the instruction. This happens regardless of whether
the operation was successful or not.
A USAGE_ERROR exception is raised if an instruction is
already active with the requested priority level (high or
low).
XOR one memory block with another memory block. The
input to the instruction are two memory blocks, both of
size C bytes, starting at address A and E respectively.
The output is the bitwise XOR of the two memory blocks,
written to the memory location starting at address E.
The priority of the instruction is defined by P, which is
either low (if P=0) or high (if P=1).
A DPU_DONE_L or DPU_DONE_H exception is raised
when the operation completes, depending on the priority
of the instruction. This happens regardless of whether
the operation was successful or not.
A USAGE_ERROR exception is raised if an instruction is
already active with the requested priority level (high or
low).
Possible exceptions
TX_OVERFLOW
OPERAND_ERROR
USAGE_ERROR
DPU_DONE_L
DPU_DONE_H
MEMADDR_ERROR
MEMADDR_ERROR
USAGE_ERROR
DPU_DONE_L
DPU_DONE_H
MEMADDR_ERROR
USAGE_ERROR
DPU_DONE_L
DPU_DONE_H
MEMADDR_ERROR
DPU_DONE_L
DPU_DONE_H
USAGE_ERROR
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